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[VHDL-FPGA-Verilog] ac97_verilog_sourcecode

Description: AC97芯片的verilog实现，有兴趣可以研究下。verilog是一种硬件开发语言，语法与c类似。与VHDL并列为IC开发两大编程语言-AC97 chip Verilog realize, who are interested can study. Verilog is a hardware development language, grammar and c similar. IC with VHDL as a programming language to develop two
Platform: | Size: 124928 | Author: 小步 | Hits:

[VHDL-FPGA-Verilog] DM9000A

Description: 详细描述了DM9000A网络接口芯片的功能，对于DE2开发板上的学习很有帮助。还上载了C程序的实现以及Verilog 代码的实现，-DM9000A described in detail the functions of network interface chip, for DE2 development board very helpful. Also upload a C procedure, as well as realize realize Verilog code,
Platform: | Size: 2657280 | Author: 周莹 | Hits:

[SCM] RedLogic_8019

Description: 使用RTL8019芯片进行以太网通讯的VERILOG源代码.-RTL8019 Ethernet chip to use the Verilog source code for communications.
Platform: | Size: 15483904 | Author: yan | Hits:

[Graph Recognize] saa7113shipincaiji

Description: 视频图像采集verilog HDl源程序，视频解码芯片部分的，可以供参考-Video image acquisition verilog HDl source, part of the video decoder chip, you can for reference
Platform: | Size: 8192 | Author: 穆垚 | Hits:

[VHDL-FPGA-Verilog] 16550

Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
Platform: | Size: 10240 | Author: David.Mr.Liu | Hits:

[Other] ad7656

Description: ad7656采样的程序，适合FPGA应用，按照芯片资料的时序进行编写-AD7656 sampling procedures, suitable for FPGA applications, in accordance with the chip timing data for the preparation of
Platform: | Size: 1024 | Author: 周海旭 | Hits:

[VHDL-FPGA-Verilog] maxII_verilog_ps2

Description: verilog语言在maxII的cpld芯片上实现ps2功能源代码-Verilog language in maxII the CPLD chip ps2 function source code
Platform: | Size: 479232 | Author: nedazq | Hits:

[VHDL-FPGA-Verilog] sram_control

Description: verilog编写fpga与片外SRAM通信模块-Verilog FPGA with the preparation of SRAM chip communication module
Platform: | Size: 418816 | Author: 宇天 | Hits:

[USB develop] logic

Description: SRAM和USB芯片FT245的VERILOG逻辑控制-USB chip SRAM and logic control VERILOG the FT245
Platform: | Size: 2048 | Author: zly | Hits:

[Other] GC4016

Description: GC4016 DDC Chip GC4016
Platform: | Size: 211968 | Author: 张晋 | Hits:

[Program doc] clock

Description: verilog编写的时钟控制程序，在xilinx芯片上开发。具有案件防抖等考虑，-Verilog clock control procedures to prepare, in the Xilinx chip development. Anti-shake, such as with the case considered
Platform: | Size: 10240 | Author: 王忠 | Hits:

[MiddleWare] counter

Description: 基于CPLD的计数器 实现光纤测距，包含与单片机的时序控制 Verilog 实现 通过仿真-CPLD-based counters realize optical ranging, single-chip microcomputer that contains timing control and realize the adoption of Verilog simulation
Platform: | Size: 2048 | Author: 强冰 | Hits:

[Software Engineering] 24c512

Description: AT24C512是ATMEL公司新近推出的具有I2C总线容量达512Kbit（64K×8）的E2PROM，该芯片的主要特性如下：存储容量为65536byte；与100kHz、400kHz、1MHzI2C总线兼容；100000次编程/擦写周期；单电源、读写电压为1.8V～5.5V；ESD保护电压>4kV；数据可保存40年；写保护功能，当WP为高电平时，进入写保护状态；CMOS低功耗技术，最大写入电流为3mA；128byte页写入缓存器；自动定时的写周期；具有8引脚DIP及20引脚SOIC封装等多种封装形式。-ATMEL Corporation AT24C512 is a newly launched I2C bus has a capacity of 512Kbit (64K × 8) of the E2PROM, the chip s main characteristics are as follows: storage capacity for 65536byte with 100kHz, 400kHz, 1MHzI2C Bus compatible 100000 times Programming/rub write cycle single-supply, read and write voltage of 1.8V ~ 5.5V ESD voltage protection> 4kV data can be stored for 40 years write-protect function, when WP is high when entering the write-protected status CMOS low-power technology, Maximum write current of 3mA 128byte page write buffer auto-timing write cycle with 8-pin DIP and 20-pin SOIC package and other packages.
Platform: | Size: 43008 | Author: zhangdi | Hits:

[Software Engineering] dma

Description: DMA调试经验，NIOS II环境下，适用altera公司芯片-DMA debugging experience, NIOS II environment, the application of altera-chip companies
Platform: | Size: 1024 | Author: yeyoushi | Hits:

[VHDL-FPGA-Verilog] SPI_AT45DB041B

Description: 用verilog编写的SPI程序,SPI芯片是AT45DB041B.文件内包含程序仿真时的截图.包括read和wirte.-SPI prepared using Verilog procedures, SPI chip AT45DB041B. Document contains procedures for simulation screenshot. Including read and wirte.
Platform: | Size: 77824 | Author: 温海龙 | Hits:

[VHDL-FPGA-Verilog] T2_USB_IN

Description: usb芯片cy7c68013从fpga中读入数据的演示程序，verilog语言-CY7C68013 chip usb read from the FPGA into the data presentation process, verilog language
Platform: | Size: 246784 | Author: ones | Hits:

[Software Engineering] pld

Description: 利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER， 设计一个20bit的up_only COUNTER, 要求该COUNTER在FE0FA和FFFFF之间自动循环计数； 分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、 EPF10K70RC240-4几种芯片中的最大工作频率； 请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来 （仅EPF10K70RC240-4芯片,最大允许Clock频率下）。-QuartusII use the MegaWizard Plug-In Manager , the design of the input data width is 4bit the ADD, SUB, MULT, DIVIDE, COMPARE them as a project, DEVICE selected EPF10K70RC240-4, on their timing simulation, the simulation waveform (input output selected group) in a paper print out. 2. QuartusII use the MegaWizard Plug-In Manager in LPM_COUNTER, the design of a 20bit of up_only COUNTER, requested that the COUNTER in FE0FA and automatic cycle count between FFFFF analysis of the COUNTER in EPM7128SLC84-7, EPM7128SLC84-10, and EPF10K70RC240-2, EPF10K70RC240-4 Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency).
Platform: | Size: 31744 | Author: 李侠 | Hits:

[VHDL-FPGA-Verilog] photo_verilog

Description: verilog开发的电子相册系统，是基于Altera的FPGA芯片和IP核的设计！-Verilog developed electronic album system is based on Altera s FPGA chip and IP core design!
Platform: | Size: 21504 | Author: sq | Hits:

[VHDL-FPGA-Verilog] PS_2

Description: 此模块用于"PS/2接口的鼠标或键盘"与"具有外部读写的8位并口单片机"双向通信模块. Verilog HDL语言编写,在Quartus II 8.1 (32-Bit)软件中编译,并下载至EPM7128SLC84-10芯片中通过. 文件中有详细的注解. 此模块具有对于PS/2时钟和数据线的滤波功能,这样减少外部干扰，保证通信的可靠性！ -This module for the "PS/2 mouse or keyboard interface" and "read and write with an external parallel port single-chip 8" two-way communication module. Verilog HDL language, in the Quartus II 8.1 (32-Bit) software compiler and downloaded to EPM7128SLC84-10 chip through. document detailed comments. This module has the PS/2 clock and data line filtering, so that to reduce the external interference, and ensure the reliability of communication!
Platform: | Size: 5120 | Author: yuantielei | Hits:

[SCM] USB_kz

Description: 提供Cy7C68013 USB芯片开发源程序，由verilog编写-Cy7C68013 USB chip to provide the development of source code, prepared by the Verilog
Platform: | Size: 1024 | Author: sky | Hits:
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